As one of conventional fault location estimation systems for multiple faults, reference is made to the fault location estimation system disclosed in Patent Document 1. This fault location estimation system estimates multiple fault locations in a logic circuit by grouping the related internal nodes for each error-observation node where a fault is detected during the test of the logic circuit, performing a single-fault-assumed fault simulation for each internal node, and finding a combination that accounts for entire error outputs.
The fault location estimation system of the related art will be described with reference to FIG. 19. Referring to FIG. 19, the fault location estimation system comprises an input device 1 that has a keyboard or an external interface unit, a data processing device 2 that operates under program control, a storage device 3 such as a hard disk or a memory where information is stored, and an output device 4 such as a display or a printer that is an external interface unit.
The storage device 3 comprises a logic circuit information storage unit 41, a fault candidate storage unit 45, and an error relation node group storage unit 46.
The logic circuit information storage unit 41 stores the following information:
logic states of signal lines;
logic states (expected values) of signal lines when the circuit is normal; and
information on error-observation nodes where an error signal is detected in a test.
The logic circuit information storage unit 41 also stores the information on the configuration of a logic circuit, that is, the following information:
gate type;
connection between gates;
connection between gate and signal line; and
connection between signal lines.
The nodes in a circuit mean the following parts that constitute the circuit as follows:
gate;
gate terminal;
net
circuit terminal
An error-observation node means one of the following at which the logic state of a circuit can be observed:
external output terminal of a circuit; and
scan flip flop (Scan-FF).
The fault candidate storage unit 45 stores the following:
fault candidates extracted by fault simulation; and
fault type of fault candidates.
The error relation node group storage unit 46 stores the result of the grouping of the nodes in a logic circuit.
The data processing device 2 comprises initialization means 21, fan-in cone classification means 27, in-node-group fault candidate extraction means 28, and error-observation node checking means 33.
The initialization means 21 references the logic circuit information storage unit 41 to set
logic circuit type; and
logic states of input/output terminals
for initializing the logic states of the signal lines.
The fan-in cone classification means 27 references the logic circuit information storage unit 41, and performs the fan-in trace beginning at each error-observation node, groups the traced nodes in the circuit according to error-observation nodes, and stores the grouped nodes in the error relation node group storage unit 46.
The in-node-group fault candidate extraction means 28 references the logic circuit information storage unit 41 and the error relation node group storage unit 46 to extract signal lines for each node group, performs single-fault simulation by referencing the logic states of the signal lines stored in the logic circuit information storage unit 41 on the assumption that a fault occurred, and stores signal lines, via which the fault propagates to an error-observation node related to the node group, in the fault candidate storage unit 45 as fault candidates.
The error-observation node checking means 33 references the logic circuit information storage unit 41 and the error relation node group storage unit 46 to calculate a combination of node groups that account for all error-observation nodes where an error was detected by the test result, and outputs the nodes of the node groups, included in the combination, to the output device 4 as fault candidates by referencing the fault candidate storage unit 45.
FIG. 20 is a flowchart showing the operation of the conventional fault location estimation system for multiple faults. Next, the following describes the operation of the conventional system in detail with reference to FIG. 19 and the flowchart in FIG. 20.
First, the initialization means 21 references the logic circuit information storage unit 41 to set
logic circuit type and
logic states of input/output nodes for initializing the logic states of the signal lines (step A1).
Next, the fan-in cone classification means 27 references the circuit configuration stored in the logic circuit information storage unit 41, performs the fan-in trace beginning at each error-observation node to classify the nodes into
node groups affecting only that terminal and
node groups affecting not only that terminal but also other error-observation nodes,
according to error-observation nodes and stores the classified node groups in the error relation node group storage unit 46 (step A8).
The in-node-group fault candidate extraction means 28 references error-observation nodes which are obtained as the test result,
circuit configuration, and
logic states of signal lines, all of which are stored in the logic circuit information storage unit 41, and
node group information stored in the error relation node group storage unit 46 in step A8,
performs the fault simulation on the assumption that a single-fault occurred with each node in each node group stuck at 0 or 1 and, by referencing the simulation result, stores the relation between each fault-assumed node and an error-observation node in the fault candidate storage unit 45, and stores the nodes of the same node group in the error relation node group storage unit 46 as the same fault candidate group (step A9).
The error-observation node checking means 33 references the logic configuration stored in the logic circuit information storage unit 41 and the error relation node group storage unit 46 to calculate combinations of node groups that can account for all error-observation nodes, where an error was detected in the test result, and references the fault candidate storage unit 45 to output the fault candidates of each node group to the output device 4 for each combination (step A14).
The conventional system performs the fan-in trace processing to narrow the nodes to those that may propagate an error signal to an error-observation node and, considering its combination, estimates multiple-fault locations.
However, the fan-in trace of a recent LSI circuit with millions of gates results in a huge number of combinations, for example, ten thousand nodes, even if the number of combinations is narrowed to one hundredth. So, the conventional system, if applied to a large-scale circuit, requires a huge amount of calculation and an impractical diagnostic time.
In the conventional system, the results of fault simulation, which assumes single fixed faults, are combined for checking with actual measurements. However, when multiple faults occur at the same time, the propagation path may differ from that of a single fault because the error propagating paths affect each other. In this case, because the multiple-fault combination that accounts for all error outputs cannot be found, the diagnostic accuracy may be reduced.
In addition, the checking of fault simulation, which assumes a single fixed-fault, with actual measurements cannot be applied to a fault mode other than that for a fixed error.
Because the fault location estimation result is output as a combination of nodes, no indication is given as to which candidate node the physical analysis priority should be given. This is especially true when the diagnosis of a large-scale circuit produces many output results.
[Patent Document 1] Japanese Patent Kokai Publication No. JP-A-11-52023
The following analysis is given by the present invention. The entire disclosure of the above mentioned Patent Document is herein incorporated by reference thereto.
A first problem with the conventional system is that it takes long to process a large scale circuit.
The reason is that the method according to the conventional technology performs the fault simulation for all nodes in a node group, generated by the fan-in trace, and checks the simulation result with the test result that is the actual measurements and, therefore, requires a longer diagnosis time as the number of nodes increases. Because the nodes are classified into groups based only on the circuit connections, the fault simulation result and the test result (actual measurements) must be compared considering the combination of all nodes in the fan-in cone. So, when the nodes to be processed are increased, the number of combinations is increased exponentially.
A second problem with the conventional system is that there is a possibility that the accuracy of multiple fault estimation will decrease.
The reason is that the conventional system, which considers only the relation between fault candidate nodes and error-observation nodes with no consideration for the error propagating paths, does not consider the possibility that multiple faults occur at the same time and their propagation paths affect each other.
A third problem with the conventional system is that the system cannot process the fault modes other than the fixed fault mode.
The reason is that the system performs the fan-in trace using the circuit connection information to classify the nodes into groups and checks the single-fault-assumed single-fault simulation results with the actual measurements for estimating fault locations. Therefore, the system cannot process fault modes other than the fixed fault mode.
A fourth problem with the conventional system is that it is difficult to carry out an actual analysis using the output result.
The reason is that, because the fault location estimation result is output as a combination of nodes, no indication is given as to which candidate node the physical analysis priority should be given. This is especially true when the diagnosis of a large-scale circuit produces many output results.